This invention generally concerns high-speed bipolar devices, and in particular, a bipolar device having a silicon germanium (SiGe) base region formed in a epitaxial (EPI) reactor process.
The integration of SiGe into the silicon bipolar base processing has been of interest because of the resulting improvements in electrical properties such as transmit frequency (Ft), Early voltage (Va), and collector-to-emitter breakdown (BVceo). The band gap at the collector side can be reduced by substituting germanium (Ge) for silicon (Si) in the base region of a bipolar transistor. This results in an electric field in the base, which reduces the majority carriers transit time through the base. SiGe films can be integrated into silicon processing with much less difficulty than other materials. However, even the use of structurally similar materials creates lattice mismatches on the crystal boundary area. Further, the formation of very thin base regions is complicated by the fact that boron implantation, even at an energy as low as 5 Kev, can still penetrate 1000 xc3x85, into the base collector junction.
Different techniques have been proposed to integrate SiGe into the base of a bipolar device. These techniques are classified into two categories: blanket SiGe film deposition and selective SiGe film deposition. The blanket SiGe deposition-method produces less silicon defects, and, therefore, higher yields. Thin, heavily doped, film can be produced with this method using growth rates of 25 to 100 xc3x85 per minute. However, blanket deposition processes are difficult to integrate into standard bipolar fabrication processes. Undesired areas of SiGe cannot easily be etched away without damaging the thin, intended base region. Alternately, selective deposition techniques can be used to form base electrode and base region underlying the emitter.
Selective deposition process can be used to grow SiGe only on silicon areas. Although selective SiGe film deposition is conceptually simple, there are additional problems associated with defect formation near the emitter-base junction.
It would be advantageous if a simple, low cost, process could be developed for the formation of SiGe base regions in a bipolar transistor.
It would be advantageous if a SiGe base region could be formed through other processes, simpler than those of selective deposition. Further, it would be advantageous if SiGe grown through an EPI reactor process could be used to form the base region of a transistor.
It would be advantageous if an emitter region and base electrode could be formed overlying a layer of blanket deposited SiGe.
Accordingly, a high-speed bipolar device is provided. The bipolar device comprises a collector region made through any conventional process. A SiGe base region overlies the collector region, formed through an EPI reactor process, to a thickness in the range of approximately 100 xc3x85 to 1000 xc3x85. A base electrode, at least partially, overlies the SiGe base region. The emitter region partially overlies extrinsic regions of the base electrode, and is connected to intrinsic regions of the SiGe base region. A silicon contact link connects extrinsic regions of the base electrode to the SiGe base region.
A temporary first oxide spacer is initially formed between the base electrode and the SiGe base region. The silicon contact link is formed after the removal the temporary first oxide spacer.
A method for fabricating a high-speed bipolar device has also been provided. The method comprises the steps of:
forming a silicon germanium compound (SiGe) base region deposited in an EPI reactor process;
forming a base electrode having an extrinsic region underlying a subsequently formed emitter;
forming a contact link from extrinsic regions of the base electrode to the SiGe base region; and
forming an emitter region overlying the SiGe base region;
A first, temporary, layer of protective oxide insulator material is formed overlying the SiGe base region. A layer of polysilicon is deposited over the first oxide layer to form the base electrode, and the first oxide layer is partially etched to form a gap between the base electrode and the SiGe base region. Silicon, or some other conductant, is isotropically deposited in the gap between the base electrode and the SiGe base region, and undesired conductant material is removed with an anisotropic process.